Basic Logic Questions

Question 1. Bit packing

A designer wants a SystemVerilog 32-bit variable instruction with three fields:

• opcode: Bits [31:16], an operation code (opcode).
• rega: Bits [15:8], a first register address.
• regb: Bits [7:0], a second register address.

1. What data type should instruction have?
2. Write SystemVerilog code to extract the fields opcode, rega, and regb from instruction into separate variables. Make sure to declare the variable types.

Question 2. Two's complement

Consider 8-bit two's-complement numbers. For each of the following decimal values, write the corresponding 8-bit two's-complement binary representation, meaning list the 8 bits for each number. Make sure to include leading zeros to show all 8 bits.

1. +13
2. -13
3. +64
4. -64
5. -1

Question 3. Literals to binary

Convert each of the following SystemVerilog literals into their 8-bit binary values. For negative values, give the 8-bit two's-complement representation.

1. 8'd13
2. 8'hF2
3. -5
4. 8'd-20
5. 8'h7F

Question 4. Truncation

Truncate the following numbers to 4 bits in both unsigned and signed representations. Provide the decimal value of the truncated numbers in each case.

1. 9
2. 15
3. 23
4. -1
5. -12

Question 5. Addition overflow

Consider the addition:

logic signed [3:0] a = A;
logic signed [3:0] b = B;
logic signed [W-1:0] c;
c = a + b;

For each of the following values of A, B, and W, determine the value of c in decimal.

1. A = 5, B = 3, W = 4
2. A = 5, B = 4, W = 4
3. A = 9, B = -7, W = 5

Question 6. Addition with multiple numbers

Consider the addition:

logic signed [7:0] a, b, c, d;
logic signed [W-1:0] sum = a + b + c + d;

What value of W is required to ensure that no overflow occurs in the sum?

Question 7. Multiplication overflow

Consider the multiplication:

logic signed [3:0] a = A;
logic signed [3:0] b = B;
logic signed [W-1:0] c;
c = a * b;

For each of the following values of A, B, and W, determine the value of c in decimal.

1. A = 3, B = 4, W = 6
2. A = 7, B = 7, W = 5
3. A = -9, B = 5, W = 6

Question 8. Arithmetic shifts

Suppose x is the SystemVerilog variable:

logic signed [7:0] x;

Use arithmetic shifts to implement each of the following operations. For each case, choose an appropriate signed bit-width for y so that no bits are lost during left shifts.

1. y = 4 * x
2. y = x / 16
3. y = 32 * x

Question 9. Bit growth and arithmetic

Consider the function:

y = 354 + x * x / 8

where x is a signed 16-bit integer (logic signed [15:0] x).

1. Determine the minimum signed bit-width required for y so that the result never overflows for any valid 16-bit signed input x.
2. Write a SystemVerilog module that implements this function using purely combinational logic. Be sure to declare all intermediate signals with appropriate widths.

Question 10. AI prompt design

You want a combinational hardware module that implements the function:

y = max{ a0*x + b0, a1*x + b1 }

Write an example prompt that you could give an AI agent so that it will generate a single, unambiguous SystemVerilog module implementing this function. Your prompt must specify enough details (such as bit-widths, signedness, precision, and combinational behavior) so that only one functional outcome is possible. There are many correct answers — the key is to be specific.