Sequential Logic and FSMs Questions

Question 1. Sequential updates

Consider the following SystemVerilog code:

always_ff @(posedge clk) begin
    x <= x + v;
    if (x > 30) begin
        v <= -10;
    end else if (x < 0) begin
        v <= 10;
    end
end

Starting from \( (x,v) = (15,10)\), what are the values of \( (x,v) \) for the next 5 clock cycles?

Question 2. Linear system

Consider the following SystemVerilog code:

always_ff @(posedge clk) begin
    x1 <= ((5*x1 + 3*x2)>>3);
    x2 <= ((4*x1 - 4*x2)>>3);
end

Here >>3 denotes a right shift by 3 bits (division by 8), and all values are 32‑bit signed integers.

1. Suppose that \((x_1,x_2) = (8,0)\). What is the value of \((x_1,x_2)\) in the next clock cycle? Remember that assignments (<=) are non‑blocking, so they update in parallel.
2. Write a Python function, say sim_lin_sys, that simulates this linear system with initial conditions x1_0 and x2_0 for nit clock cycles and outputs the values in an array X of shape (nit+1, 2). The first row of X should be the initial conditions.

Question 3. ReLU function

ReLU function: We wish to implement the function

\( y = a x^2 + \max\{ b x, 0 \} + c \)

for an input x and constants a, b, and c. Write the SystemVerilog code to implement this function over two clock cycles. Specifically, the input x should be registered in the first clock cycle, and the output y should be produced in the second clock cycle. Make sure that no clock cycle requires two or more multiplications that cannot be parallelized. You do not need to include the module declaration, or declaration of variables; just the always_ff and always_comb blocks.

Question 4. ReLU+quadratic

Consider the following SystemVerilog code:

always_comb begin
    act_in = w1*xreg + b1;
    if (act_in > 0) begin
        a = act_in;
    end else begin
        a = 0;
    end
    xsq = ((xreg*xreg) >> 2);
    y = xsq + w2*a + b2;
end

always_ff @(posedge clk) begin
    xreg <= x;
end

Here, >> 2 denotes a right shift by 2 bits (division by 4). The code registers the input x into xreg on each clock cycle and produces the output y in a single clock cycle based on the registered value.

Assume that w1, b1, w2, and b2 are constants. Rewrite the code so that it operates over two clock cycles. Specifically, register the input x on the first clock cycle, and compute the output y two clock cycles later. This requires introducing additional registers to store intermediate values. You do not need to include the module declaration, or declaration of variables; just the always_ff and always_comb blocks.

Question 5. Bouncing ball

We simulate a ball moving in one-dimensional space between two walls at positions 0 and 100. The ball has a position x and a velocity v. At each time step, the ball first moves according to its velocity:

\( x \gets x + v \)

If this motion causes the ball to go past a wall, the ball “bounces” and reverses direction. The bounce should behave the same way a real ball would: the ball cannot pass through the wall, and the rebound distance should be consistent with how far it would have travelled past the wall.

For example:

• If \((x,v) = (40,10)\), then the ball moves to \(50\), which is inside the interval, so the next state is \((50,10)\).
• If \((x,v) = (96,10)\), then the ball would move to \(106\), which is past the right wall at \(100\). After bouncing, the ball ends up at position \(94\) with velocity \(-10\).
• If \((x,v) = (3,-10)\), then the ball would move to \(-7\), which is past the left wall at \(0\). After bouncing, the ball ends up at position \(7\) with velocity \(10\).

Write the SystemVerilog code for the updates for x and v. You do not need to include the module declaration, just the always_ff and always_comb blocks.

Question 6. Exponent

Suppose we wish to implement the function

\( y = x^i \)

where the exponent \(i\) is an integer in the set \(\{0,1,2,3\}\). The input x and output y are signed 32-bit integers (you do not need to worry about overflow).

Write SystemVerilog code that computes y. The output should always be produced exactly two cycles after the input, even when \(i = 0\), \(1\), \(2\), or \(3\). If two multiplications are in the same clock cycle, they must be parallelizable. You do not need to include the module declaration, or declaration of variables; just the always_ff and always_comb blocks.

Hint: You will need to use delay lines to store the input x and exponent i. This problem requires pipelining, which we will discuss in more detail in later units.

Question 7. Testbench code

A SystemVerilog testbench instantiates an instance dut, of the module my_func, to compute a function \( y = f(x) \):

// Testbench signals
logic signed [31:0] x;
logic signed [31:0] y;
logic clk;

// Instantiate the device under test (dut)
my_func dut (
    .clk(clk),
    .rst(rst),
    .x(x),
    .y(y)
);

// Test vectors
logic signed [31:0] xtest [0:3] = '{10, 20, -5, 7};

Write an initial block that:

• On cycle 0, sets rst = 1, then de‑asserts it on the next cycle.
• Starting on cycle 4, sets x = xtest[0] and prints the output y on cycle 8.
• On cycle 9, sets x = xtest[1] and prints y on cycle 13.
• On cycle 14, sets x = xtest[2] and prints y on cycle 18.
• Continue similarly for the remaining test inputs.

To display a number, you may use:

$display("x = %0d", x);

Question 8. AI prompt design - sequential counter

You want to create a counter module in SystemVerilog that counts from 0 to a specified maximum value. Provide a prompt to an AI that clearly describes the requirements for this counter module. Your prompt should be written as if you are instructing the AI to generate the SystemVerilog code.

Your prompt must specify the module’s inputs, outputs, and cycle-by-cycle behavior with minimal ambiguity. In particular, you should clearly describe:

• The clock and reset inputs, including whether reset is synchronous or asynchronous and its polarity.
• How the counter is started (e.g., a start signal), including how that signal is sampled and interpreted (pulse vs. level, what happens if it stays high, etc.).
• How the final (maximum) count value is specified (e.g., parameter vs. input port) and what happens when the counter reaches that value (stop, hold, wrap, done pulse, etc.).
• The relevant bit widths for the counter, maximum value, and any status signals.
• The exact behavior on reset (what values are cleared, what happens if reset occurs mid-count, and when outputs become valid again).
• The timing of outputs relative to the clock (e.g., registered outputs, when done asserts and deasserts).

There is no single correct solution. However, your prompt should be sufficiently detailed that the exact cycle-by-cycle behavior of the counter is clear to the AI and to a human reading your specification.