A FIFO buffer stores commands with three elements, here ap_int represents an arbitrary bit-width integer type
with n bits.
struct Command {
ap_int<16> command_id;
ap_int<32> operand1;
ap_int<32> operand2;
};
A producer writes data elements A, B, and C into a FIFO buffer at clock cycles 0, 1, and 6, respectively. Data can be read from the FIFO on the clock cycle immediately after it is written (for example, data element A can be read starting at clock cycle 1). Once a consumer reads an element, it takes 2 clock cycles to process it before the consumer can read the next element from the FIFO. Assuming the consumer attempts to read from the FIFO as soon as possible and starts at clock cycle 1, at which clock cycles will the consumer read:
A producer generates data elements A, B, C, and D. The earliest clock cycles at which each element becomes available for writing into a FIFO are:
The FIFO has a capacity of 2 elements. A write can occur only if the FIFO is not full. If the FIFO is full when an element becomes available, the producer must stall and retry the write on each subsequent cycle until it succeeds.
A consumer reads one element at a time from the FIFO. If data is written on cycle N, it is available to be read and removed from the FIFO on cycle N+1, and will process the element until cycle N+3. Thus, the next read is possible at cycle N+4.
For each element, determine the clock cycle at which the write actually succeeds ( i.e., when the element is stored in the FIFO) and when the processing is complete.
A computer vision accelerator processes a stream of video frames. Each frame requires 5 ms of base processing time. On 10% of the frames, an object of interest is detected. For these frames, the accelerator requires an additional 100 ms of processing time (for a total of 105 ms on those frames). The accelerator processes frames one at a time.
Assume frames arrive continuously and the accelerator must keep up with the input stream without the input FIFO growing without bound.
An AXI4-Stream master has data elements A, B, C, and D. The earliest they can be transferred are:
The slave has no FIFO size limit and therefore always asserts
TREADY = 1. However, the slave can only consume one element
every 2 cycles with a 1 cycle delay after it is written:
Fill in the following table for cycles 0–8. In the Write action
column, indicate whether the master transfers an element or is idle.
For example, transfer A or idle.
Similarly, in the slave action column, indicate whether the slave reads, processes, or is idle.
For example, read A, process A,
or idle.
| Cycle | Write Action (transfer or idle) | TVALID | FIFO State after read/write | Slave Action (read, process, or idle) |
|---|
Assume the FIFO starts empty. Note that you do not need to
show TREADY for each cycle since it is always asserted.
If you are writing the solution in the solution box, any
format is acceptable. For example, for the first row you can write:
Cycle 0: Write A, TVALID=1, FIFO=[A], Slave=Idle
or even, since the columns are known, you can just write the values:
0: Write A, 1, [A], Idle
A master on an AXI4-Stream interface writes 10 data elements (1st, 2nd, ..., 10th)
beginning on clock cycle 0. The slave has a large FIFO, so it always asserts
TREADY = 1, and therefore the master successfully transfers one element
per cycle for 10 cycles.
The slave behavior is non-pipelined:
Assume the slave starts idle and attempts to read and process elements as soon as possible.
An AXI4-Stream master has data elements A, B, C, and D that
are all available for transfer at cycle 0.
The slave has an input FIFO of depth 2.
The slave asserts TREADY = 1 whenever the FIFO is not full.
If the FIFO becomes full in cycle n, then
TREADY = 0 in cycle n+1.
The slave consumes data as follows:
Fill in the following table for cycles 0–8.
In the Write Action column, indicate whether the master transfers an element or stalls.
For example, transfer A, Write A stall or
idle. In the Slave Action column, indicate whether
the slave reads, processes, or is idle.
For example, read A, process A, or idle.
The FIFO starts empty.
| Cycle | Write Action (transfer, stall or idle) | TVALID | TREADY | Slave Action | FIFO State after read/write | TREADY_next |
|---|
You are given the following AXI4‑Stream timing table.
A transfer occurs on any cycle where TVALID = 1 and TREADY = 1.
| Cycle | TREADY | TVALID | TLAST |
|---|---|---|---|
| 0 | 0 | 0 | 0 |
| 1 | 1 | 1 | 0 |
| 2 | 0 | 1 | 0 |
| 3 | 1 | 1 | 0 |
| 4 | 0 | 1 | 1 |
| 5 | 1 | 1 | 1 |
TVALID = 1)?You are given a command header with the following data structure. Here
ap_uint represents an unsigned integer with n bits, and
ap_fixed represents a signed fixed-point value with W total bits
and I integer bits (including the sign bit).
class CmdHdr {
ap_uint<16> trans_id; // Transaction ID
// Rotation angles in Q12.10 format, where 1.0 corresponds to π radians
ap_fixed<12,1> yaw, pitch, roll;
ap_uint<16> nsamp; // Number of samples to rotate
};
void serialize(const CmdHdr &cmd_hdr, ap_uint<32> words[/* fill in */]) {
...
}
You are given the same command header structure as in the serialization problem.
Here ap_uint represents an unsigned integer with n bits, and
ap_fixed represents a signed fixed‑point value with W total bits
and I integer bits (including the sign bit).
class CmdHdr {
ap_uint<16> trans_id; // Transaction ID
// Rotation angles in Q12.10 format, where 1.0 corresponds to π radians
ap_fixed<12,1> yaw, pitch, roll;
ap_uint<16> nsamp; // Number of samples to rotate
};
The header has been serialized into three 32‑bit words using the packing shown in the table below. No field crosses a 32‑bit boundary.
| Word | Bits | Field | Width |
|---|---|---|---|
| Word 0 | 15:0 | trans_id | 16 bits |
| 27:16 | yaw | 12 bits | |
| Word 1 | 11:0 | pitch | 12 bits |
| 23:12 | roll | 12 bits | |
| Word 2 | 15:0 | nsamp | 16 bits |
CmdHdr object.cmd_hdr.void deserialize(CmdHdr &cmd_hdr, ap_uint<32> words[3]) {
// Fill in your solution here
}