Timing and Critical Paths Questions

Question 1. Propagation delay

A signal \(x\) changes according to the following table:

Time [ns]102030
Value042

So, \(x=0\) starting at 10 ns, \(x=4\) starting at 20 ns, and \(x=2\) starting at 30 ns. The signal is passed through a circuit whose stable value is \(y = 2x + 1\) with a propagation delay of 3 ns. List the times at which \(y\) changes and the corresponding values. Ensure to mark the period of unknown values (i.e., \(y=?\) appropriately.

Question 2. Series timing

Consider the following SystemVerilog combinational code:

xsq = x*x;
y = a*xsq;
z = y + b;

Assume each multiplication has a maximum propagation delay of 3 ns and the addition has a maximum propagation delay of 2 ns. Suppose that x is stable for a long period before time 0, and then changes immediately to x=4 at time 10 ns, remaining stable thereafter. The variables a=3 and b=6 are constants. Answer the following:

  1. What are the stable values for xsq, y, and z before and after the change?
  2. After the switch at \(t=10\) ns, at what point do each of the signals first become stable, and when do they reach their final stable values?

Question 3. Multi-path timing

Consider the following SystemVerilog combinational code:

z1 = a*x;
z2 = x+b;
y = max(z1, z2);

Suppose that the input \(x\) changes with the following times and values:

Time [ns]01012
Value0?4

Specifically, the input \(x\) is stable at 0 for a long period before time 0, then changes to an unknown value (?) at 10 ns, and then becomes stable again at 4 starting at 12 ns. The variables \(a=3\) and \(b=6\) are constants. Assume that the multiplication has a maximum propagation delay of 3 ns, the addition has a maximum propagation delay of 2 ns, and the max operation has a maximum propagation delay of 1 ns. Answer the following:

  1. What are the stable values for z1, z2, and y before t=10 ns?
  2. What are the eventual stable values after t=12 ns after all propagation delays?
  3. What times after t=10 ns do the signals z1, z2, and y first become unknown (?) and then stable again?

Question 4. Timing with multiplexer

Consider the following SystemVerilog combinational code with two inputs, \(x_1\) and \(x_2\):

if (x1 > 2) begin  // Delay to evaluate condition = 0.5 ns
    z1 = func1(x1);  // propagation delay of 4 ns
end else begin
    z1 = func2(x1);  // propagation delay of 2 ns
end
z2 = func3(x2);   // propagation delay of 3 ns
y = func4(z1, z2);  // propagation delay of 1.5 ns

The if condition is implemented with a multiplexer, meaning both functions \(f_1\) and \(f_2\) are evaluated in parallel, but only one of their outputs is selected based on the value of \(x_1\). The multiplexer has a propagation delay of 0.8 ns. Suppose that before time 0, all signals are stable, and then at time 0, both \(x_1\) and \(x_2\) change value simultaneously. At what point do the following signals become stable (i.e., no longer unknown):

  1. \(z_1\)
  2. \(z_2\)
  3. \(y\)

Question 5. Critical path

Consider the following SystemVerilog code:

always_comb begin
    x1_next = func1(x1); // delay = 2.3 ns

    // mux delay = 0.4 ns
    if (x1 > 2) begin  // delay = 0.5 ns
        x2_next = func2(x1);  // delay = 3.7 ns, depends on x1
    end else begin
        // delay = 2.1 ns, depends on x1_next, not x1
        x2_next = func3(x1_next);  
    end
end
always_ff @(posedge clk) begin
    x1 <= x1_next;
    x2 <= x2_next;
end

The if condition is implemented with a multiplexer with the condition and two branches evaluated in parallel. The multiplexer adds an additional delay of 0.4 ns.

  1. Determine the critical path delay for the combinational logic that produces x1_next and x2_next.
  2. What is the maximum clock frequency for this design assuming clock-to-Q delay is 0.2ns and setup time is 0.1ns?

Question 6. Two cycle datapath

Consider the following SystemVerilog code with an input x:

always_comb begin
    xsq = xreg*xreg;  
    axsq = a*xsq;  
    bx = b*xreg;  
    if (xreg > 10) begin 
        y = axsq + bx;  
    end else begin
        y = bx;  
    end
end
always_ff @(posedge clk) begin
    xreg <= x;
end

Assume the following delays:

Answer the following:

  1. The current code computes y in a single cylce. What is the propagation time after the rising edge of the clock for the signal y to become stable (i.e., no longer unknown)?
  2. Rewrite the code registering xsq, bx, and gt10=xreg>10 to create a two cycle datapath for computing y.
  3. What is the critical path delay for the two cycle datapath?