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Hardware Design
Hardware Design
Demos
Getting Started
Basic Sequential Logic and FSMs
Fixed Point Design
Python Golden Model
System Verilog Implementation
Bus Basics and Memory‑Mapped Interfaces
Creating the Vitis IP
C Simulation and Synthesis
RTL Simulation
Packaging the Vitis IP
Building the FPGA bitstream and PYNQ Overlay
Accessing the IP from PYNQ
Command-Response FIFO Interface
Overview
Data structures
AXI4-Stream protocol
C and RTL Simulation
Loop optimization
Vector multiplier example
Initial synthesis
Pipelining
Loop unrolling
Automated parameter sweeping
Shared Memory PS Interface
Creating the Vitis IP
AXI memory transfers
Building the FPGA project
Accessing the IP from PYNQ
Support Material
Vitis and Vivado
Installing Vitis and Vivado
Windows-specific instructions
Launching Vitis and Vivado
Finding the FPGA part
Building and Simulating Projects with System Verilog Files
Building a Vivado Project with a PS
Building a Vitis HLS project
FPGA Boards
Setting up the Pynq-Z2 board
Setting up the RFSoC 4x2 board
Getting IP connectivity
GitHub Repository
Cloning the Repository
Installing the python package
NYU Remote Server
SSH connection
Fast-X GUI connection
Launching Vitis and Vivado
Using Python
NYU class
Course Units
Submitting Problem Sets
Class Project
Labs
Conditional Subtraction Division
Theory
Building a Python Model
System Verilog Implementation
Submitting the Lab
Cubic Fixed Point
Building and Validating the Python Model
System Verilog Implementation
Single Test Case
Multiple Test Cases
AI Autograder
How to use it
OpenAI Keys
Submitting on Gradescope
Search Hardware Design
Hardware Design
Demos
Demos
This folder contains a number of demos that we will use in the class.
Table of contents
Getting Started
Basic Sequential Logic and FSMs
Fixed Point Design
Bus Basics and Memory‑Mapped Interfaces
Command-Response FIFO Interface
Loop optimization
Shared Memory PS Interface