A tentative set of units is as follows. I’ve only added a few units so far, but I am hoping to get done by the end of the semester. Problem sets can also be found on the AI Grader portal, but this website is experimental.

• Course Introduction
  • Lecture: [PDF] [pptx]
  • Software and hardware set-up
• Unit 1: Data Types and Combinational Logic
  • Review of number systems from previous class
  • Lecture: [PDF] [pptx]
  • Problems
• Unit 2: Sequential Logic and Finite State Machines
  • Lecture: [PDF] [pptx]
  • SystemVerilog Demo: Simple scalar functions
  • Problems
  • Lab: Division by conditional subtraction
• Unit 3: Floating and Fixed Point Arithmetic
  • Lecture: [PDF] [pptx]
  • In-class exercise
  • SystemVerilog Demo: Fixed point implementation
  • Problems
  • Lab: Fixed point implementation of a polynomial
• Unit 4: Bus Basics and Memory-Mapped Interfaces
  • Lecture: [PDF] [pptx]
  • Vitis HLS Demo: Simple AXI4-Lite interface
• Unit 5: FIFO and Streaming Interfaces
  • Vitis HLS Demo: AXI4-Streaming FIFO interface
• Unit 6: Timing Diagrams and Critical Path Analysis
• Unit 7: Burst Transfers and Loop Optimization
  • Vitis HLS Demo: A pipelined vector multiplier
• Unit 8: FIR Filters
• Unit 9: Systolic Arrays
• Unit 10: Multi-Threaded Control
• Unit 11: Dataflow and message-passing architectures
• Unit 12: Interfacing with high-speed sample