The Command-Response FIFO Interface
In the simple scalar function example, the IP interfaced with the processor via a set of simple AXI-Lite command registers. This interface is inefficient because the processor must explicitly configure the IP before each operation. When the processor is involved in many tasks, the delay in configuring the IP can be significant. In addition, the interface we described requires periodically polling the IP, which also consumes significant overhead.
In this unit, we introduce a widely used and efficient design pattern for IPs: the command–response structure.
By working through this unit, you will learn to:
- Design command and response data structures for a simple IP
- Implement FIFO interfaces for the command and response data with AXI-Stream protocol
- Create VITIS-synthesizable serialization and deserialization methods for general data structures
- Add transaction IDs and error controls for command–response pairs
- Visualize the AXI-Stream protocols in timing diagrams