Shared Memory Interface to the Processor

In the previous unit on loop optimization, we built and optimized a simple vector multiplier IP core. We will now interconnect this IP to the PS. In this unit, we consider a simple interconnection method based on shared memory. Specifically, you will learn to:

• Add Vitis IP in a Vivado project that can read and write to external DDR memory
• Build and connect the memory interfaces with the AXI protocol
• Interact with the memory and Vitis IP from a jupyter notebook with PYNQ

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Go to Creating the Vitis IP.

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Table of contents

• Creating the Vitis IP
• AXI memory transfers
• Building the FPGA project
• Accessing the IP from PYNQ