Polynomial Accelerator

This example demonstrates an end-to-end PySilicon workflow for a small polynomial accelerator.
The key idea is that the interface is defined once in Python using PySilicon DataSchema classes, and that definition is then reused across software modeling, test-vector generation, and Vitis HLS integration.

With this flow, PySilicon helps reduce drift between Python reference code and hardware-facing C++ interfaces, while making it easier to validate the accelerator against a golden model.

In this example, we:

  • Define the request and response schemas in Python using PySilicon DataSchema classes
  • Auto-generate matching C++ headers for Vitis HLS, including serialization and deserialization support for the data schemas
  • Build a Python golden model and generate binary test vectors
  • Create a Vitis IP with AXI4-Streaming interfaces using the generated schema serialization logic
  • Create a Vitis testbench that reads and writes test vectors produced by the Python golden model
  • Run the Vitis testbench from Python using PySilicon toolchain utilities
  • Compare the Vitis outputs against the Python reference

The full example files are in examples/poly.

The main runnable script is examples/poly/poly_demo.py.

Why this example matters

This example shows how PySilicon can be used to:

  • Keep interface definitions consistent across Python and HLS code
  • Reuse the same schema description for both modeling and hardware integration
  • Generate reproducible test vectors from a Python golden model
  • Validate hardware-oriented code against a software reference
  • Move toward a more automated hardware/software co-design flow

Current limitations

This example demonstrates only part of the intended PySilicon workflow. Future versions will add:

  • A Python golden model represented as a PySilicon HwObj class that defines AXI interfaces and interface actions
  • Auto-generation of the Vitis IP and Vitis testbench code from the HwObj description

Polynomial Accelerator Protocol

This example implements a polynomial accelerator with the following protocol:

  • The host writes polynomial coefficients to the accelerator’s AXI-Lite register map (a VitisRegMap), then writes ap_start to launch the kernel
  • The host sends a PolyCmdHdr (cmd_type = DATA) containing the transaction ID and sample count over the input AXI-Stream
  • The host then streams nsamp input values (x)
  • The accelerator returns a PolyRespHdr echoing the transaction ID, then streams nsamp result values (y)
  • When the host has no more work, it sends a PolyCmdHdr with cmd_type = END to break the kernel’s persistent loop cleanly
  • On error the kernel halts: it sets halted = 1, error = <code>, tx_id = <offending txn> in the regmap and returns. The host re-launches the kernel via platform reset, then writes ap_start again

    Files used in the example

  • examples/poly/poly_demo.py drives the Python flow.
  • examples/poly/poly.hpp declares the HLS interface and includes the generated schemas.
  • examples/poly/poly.cpp implements the polynomial kernel.
  • examples/poly/poly_tb.cpp reads vectors, calls the kernel, and writes outputs.
  • examples/poly/run.tcl runs the Vitis C-simulation flow.

Go to Python flow

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