PySilicon Timing Analysis Tools

PySilicon provides some basic package for python processing of timing diagrams relevant for hardware workflows:

• Creating timing and plotting timing diagrams in matplotlib
• Running Xilinx RTL simulations to produce VCD outputs
• Extracting information from timing diagrams
• Python-based analysis for AXI protocols including AXI-Lite, AXI-Streaming, and AXI memory-mapped

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Table of contents

• Timing Diagrams
• Extracting VCD Files
• Parsing VCD Files
• AXI4-Stream Timing Analysis
• AXI4 Memory-Mapped Timing Analysis