Hardware Interfaces

PySilicon models hardware communication channels as interfaces — transactional connections between SimObj instances in a SimPy discrete-event simulation. Interfaces decouple the timing model of a bus from the functional logic of the components connected to it.

• Overview
• Streaming Interfaces
• AXI4 Memory Mapped interfaces
• Register Maps

---

Table of contents

• Overview
• Stream Interfaces
• MM Interfaces
• Register Maps
• Schema Transfer Interface
• Array Transfer Interface