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PySilicon
PySilicon
Overview
Motivation
Innovations
WaveFlow Example
Prior Work
Architecture
Hardware Objects
Simulation
Planning and Synthesis Modes
AI-Assisted Planning
Synthesis
Unit Testing
AI Assistants
Generated C/C++ APIs
RTL Verification
Guide
Installation
Installing the Python Package
OpenAI Setup
Installing the MCP Server
Semantic Example Search
Installing the VS Code Extension
Developers
Headless Testing
Memory Modeling
Using Memory in Python
Memory Interfaces in Vitis HLS
Data Schemas
Fields and Lists
Code Generation
Data arrays
Data Unions
Interfaces
Overview
Stream Interfaces
MM Interfaces
Register Maps
Schema Transfer Interface
Array Transfer Interface
Harware Components
Build System
Core Components
Code Generation Steps
Python Simulation Pattern
Vitis Pattern
Timing Analysis Tools
Timing Diagrams
Extracting VCD Files
Parsing VCD Files
AXI4-Stream Timing Analysis
AXI4 Memory-Mapped Timing Analysis
Examples
Polynomial Accelerator
Python Flow
Vitis Kernel Implementation
Vitis Testbench Implementation
AXI4-Stream Timing Analysis
Search PySilicon
PySilicon
Guide
Harware Components
Hardware Components
This section needs to be written
Represent hardware components, either in the test bench, host software, or synthesizable components of hardware
Defines a set of named interface endpoints