Labs

As part of the class, we are building a few labs in both SystemVerilog and Vitis HLS. Unfortunately, we only have a few labs so far. But, we will add more over the course of the semester.

• Unit 2: Division with conditional subtraction
  • Implement a simple integer mathematical algorithm in SystemVerilog with a FSM and a handshake protocol.
• Unit 3: Fixed point implementation of a cubic function
  • Implement a simple function in fixed point in SystemVerilog and validate against a python Golden model
• Unit 4: Root solver for a nonlinear function
  • Implement a simple iterative root solver accelerator in Vitis HLS and optionally connect to a processor.

---

Table of contents

• Conditional Subtraction Division
• Cubic Fixed Point
• Root Solver