Labs

As part of the class, we are building a few labs in both SystemVerilog and Vitis HLS. Unfortunately, we only have one lab so far. But, we will add more over the course of the semester.

• Unit 2: Division with conditional subtraction
  • Implement a simple integer mathematical algorithm in SystemVerilog with a FSM and a handshake protocol.
• Unit 3: Fixed point implementation of a cubic function
  • Implement a simple function in fixed point in SystemVerilog and validate against a python Golden model

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Table of contents

• Conditional Subtraction Division
• Cubic Fixed Point