Building the Vitis HLS IP and Testbench

We next build the Vitis HLS IP to run the Euler root solving iteration. Copy the files from:

rootsolve/partial/fsolve.cpp -> rootsolve/fsolve.cpp
rootsolve/partial/tb_fsolve.cpp -> rootsolve/tb_fsolve.cpp

Then, complete all the sections marked TODO. In fsolve.cpp, try to make the algorihm match the python. You will have to:

  • Set the #pragma statements for the AXI4-Lite interface
  • Implement the loop including the early termination condition

In the testbench, tb_fsolve.cpp, I have already implemented all the file reading and writing. You just need to write the condition to ensure that the Vitis IP matches the outputs from the python.

You now have two options to test the Vitis HLS IP and testbench:

Both methds will result in the same final outputs and will receive full credits. So, it is just your preference.

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