Hardware Interfaces

Waveflow models hardware communication channels as interfaces — transactional connections between SimObj instances in a SimPy discrete-event simulation. Interfaces decouple the timing model of a bus from the functional logic of the components connected to it.

This section is the Python transactional model: the interface classes, their master/slave endpoints, the write / read / get calls, binding, and the cycle-based latency model. It is Python-only by design — an interface is not a standalone synthesizable artifact but a port of a component, so its synthesizable side is documented where the kernel is.

Pages

  • Overview — the core model: Interface vs endpoint, the Words type, latency, and the SimPy lifecycle.
  • Stream Interfaces — unidirectional streams (StreamIF, CrossBarIF) and pipelined transfer.
  • MM Interfaces — memory-mapped read/write (AXIMMCrossBarIF, DirectMMIF).
  • Polling Overhead — the loosely-timed polling model (MMIFMaster.poll_until): bandwidth steal + discovery latency.
  • AXI-MM Command Queue — the in-memory command ring (AXIMMQueue): control moved off the stream and into shared memory.
  • Register Maps — AXI-Lite control/status fields (RegMap, VitisRegMap).
  • Schema Transfer Interface — carrying serializable schema objects over a transport.
  • Array Transfer Interface — carrying a variable-length typed array over a transport.

See also

  • Hardware Components — declaring the ports (these endpoints) on a component.
  • Custom Hooks — the synthesizable side: using an interface inside a kernel body (the #pragma HLS INTERFACE ports and the read_stream / m_axi calls on it).

Table of contents

  • Overview - The transactional interface model — Interface vs master/slave endpoint, the Words type, the cycle-based latency model, and the SimPy write/read/bind lifecycle, plus a runnable two-SimObj StreamIF toy.
  • Stream Interfaces - Unidirectional stream interfaces in the SimPy model — point-to-point StreamIF (write/rx_proc), the CrossBarIF switching fabric, and pipelined get/write timing, with a runnable two-SimObj producer→consumer toy.
  • MM Interfaces - Memory-mapped interfaces in the SimPy model — MMIFMaster/MMIFSlave endpoints, the AXIMMCrossBarIF (FULL/LITE, address routing) and DirectMMIF, and read/write/read_schema/read_array, with a runnable two-SimObj DirectMMIF toy.
  • Polling Overhead - The loosely-timed polling-overhead model — MMIFMaster.poll_until with a restricted PollCond, the per-bus bandwidth-steal (ov) derating and the deterministic discovery-latency delay, modeled in O(transactions) rather than by stepping every poll cycle.
  • AXI-MM Command Queue - The in-memory command queue — AXIMMQueue, a host-driven ring buffer over an MMIFMaster (m_axi). The AXIMMQueueLayout (head/tail/capacity + data slots), the producer write / consumer get operations, and the loosely-timed poll-on-empty / backpressure-on-full timing model.
  • Register Maps - AXI-Lite register maps in the SimPy model — RegField/RegAccess, the RegMap slave dispatch, the VitisRegMap ap_ctrl_hs (ap_start/ap_done) launch lifecycle, and the BoundRegMap host surface, with a runnable two-SimObj launch-then-poll toy.
  • Schema Transfer Interface - The logical interface that carries serializable schema objects (DataList / DataUnion) over a transport — write(obj) / rx_proc, the layered transport model, and single- vs multi-type framing, with a runnable two-SimObj toy.
  • Array Transfer Interface - The logical interface that carries a variable-length typed array over a transport — write(elements) with a numpy fast path, push (rx_proc) vs pull (get(count)) receive, and TLAST length validation, with a runnable two-SimObj toy.
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