Data Schemas — HLS

The HLS side is the synthesizable C++ Waveflow generates from a Python schema, bit-for-bit compatible with the Python model. These pages cover code generation — the C++ struct each schema becomes — serialization — moving a single schema value in and out over a packed integer, an m_axi memory port, a FIFO, or an AXI4-Stream — and test-data files, the uint32 binary bridge that carries vectors between the Python golden and the Vitis testbench.

For packing arrays of schemas — the packing factor, lanes, and the vectorized lane loop — see Vectorization.

---

Table of contents

• Code Generation - Generate the Vitis HLS C++ headers from a schema: DataSchemaStep emits a schema's struct header (+ testbench helpers), ArrayUtilsStep emits the array packing helpers for an element type, both atop the shared StreamUtilsStep.
• Serialization - Move a single schema value to and from fixed-width words — the C++ per-interface methods (pack_to_uint / read_array / read_stream / read_axi4_stream) and the Python serialize / deserialize to Words — generated from one definition so they agree bit-for-bit. Covers word_bw, nwords, the Words dtype rule, and the 8192-bit packed-integer cap.
• Test Data Files - Move test data between the Python golden and the Vitis C-sim testbench via little-endian uint32 binary files — write_uint32_file / read_uint32_file on the Python side, streamutils::{read,write}_uint32_file on the C++ side — both using the same 32-bit-word packing, so values round-trip bit-for-bit.