Waveflow Timing Analysis Tools

Waveflow provides some basic package for python processing of timing diagrams relevant for hardware workflows:

• Creating timing and plotting timing diagrams in matplotlib
• Running Xilinx RTL simulations to produce VCD outputs
• Extracting information from timing diagrams
• Python-based analysis for AXI protocols including AXI-Lite, AXI-Streaming, and AXI memory-mapped

The waveflow.utils.timing module renders two complementary views, each of which can be built by hand or from a trace: Timing Diagrams (waveforms — value boxes per transition, for a ~10–50 cycle zoom) and Activity Diagrams (activity bands + an optional occupancy panel, for the whole-run and stage-overlap view).

For a free-running (ap_ctrl_none) hls::task kernel, Tracing a kernel run covers the four build steps that dump a VCD of its internal channels and bind the signals by exact name; Trace pitfalls collects the three subtle ways such a measurement goes silently wrong (sampling phase, ap_done anchoring, occupancy vs write-enable). The memcpy timing example applies the whole flow to one kernel.

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Table of contents

• Timing Diagrams
• Activity Diagrams
• Extracting VCD Files
• Parsing VCD Files
• AXI4-Stream Timing Analysis
• AXI4 Memory-Mapped Timing Analysis
• Stream-of-Blocks Timing Analysis
• Cosim timing
• Tracing a kernel run
• Trace pitfalls